Comparative studies of pipelined circuits, Fabian Klass, Michael J. Flynn

@TechReport{csl-tr-93-579,
  author = 	 "Fabian Klass, Michael J. Flynn",
  title = 	 "Comparative studies of pipelined circuits",
  institution =  "Computer Systems Laboratory, Stanford University",
  year = 	 1993,
  address =	 "Techniccal Report No. CSL-TR-93-579"
}

Automatic technology mapping for generalized fundamental-mode asynchronous designs, Polly Siegel, Giovanni De Micheli, David Dill

@TechReport{csl-tr-93-580,
  author = 	 "Polly Siegel, Giovanni De Micheli, David Dill",
  title = 	 "Automatic technology mapping for generalized
		  fundamental-mode asynchronous designs",
  institution =  "Computer Systems Laboratory, Stanford University",
  year = 	 1993,
  address =	 "Techniccal Report No. CSL-TR-93-580"
}

Incremental tools for the design and verification of VLSI circuits, Arturo Salz

@TechReport{csl-tr-93-581,
  author = 	 "Arturo Salz",
  title = 	 "Incremental tools for the design and verification of
		  VLSI circuits",
  institution =  "Computer Systems Laboratory, Stanford University",
  year = 	 1993,
  address =	 "Techniccal Report No. CSL-TR-93-581"
}

Optimization of combinational logic circuits based on compatible gates, Maurizio Damiani, Jerry Chih-Yuan Yang, Giovanni De Micheli

@TechReport{csl-tr-93-584,
  author = 	 "Maurizio Damiani, Jerry Chih-Yuan Yang, Giovanni De Micheli",
  title = 	 "Optimization of combinational logic circuits based
		  on compatible gates",
  institution =  "Computer Systems Laboratory, Stanford University",
  year = 	 1993,
  address =	 "Techniccal Report No. CSL-TR-93-584"
}

The interaction of virtual memory and cache memory, William L. Lynch

@TechReport{csl-tr-93-587,
  author = 	 "William L. Lynch",
  title = 	 "The interaction of virtual memory and cache memory",
  institution =  "Computer Systems Laboratory, Stanford University",
  year = 	 1993,
  address =	 "Techniccal Report No. CSL-TR-93-587"
}

Update-based cache coherence protocols for scalable shared-memory multipocessors, David B. Glasco, Bruce A. Delagi, Michael J. Flynn

@TechReport{csl-tr-93-588,
  author = 	 "David B. Glasco, Bruce A. Delagi, Michael J. Flynn",
  title = 	 "Update-based cache coherence protocols for scalable
		  shared-memory multipocessors",
  institution =  "Computer Systems Laboratory, Stanford University",
  year = 	 1993,
  address =	 "Techniccal Report No. CSL-TR-93-588"
}

The effect of fault dropping on fault simulation time, Rong Pan, Nur A. Touba, Edward J. McCluskey

@TechReport{csl-tr-93-590,
  author = 	 "Rong Pan, Nur A. Touba, Edward J. McCluskey",
  title = 	 "The effect of fault dropping on fault simulation time",
  institution =  "Computer Systems Laboratory, Stanford University",
  year = 	 1993,
  address =	 "Techniccal Report No. CSL-TR-93-590"
}

Logic synthesis for concurrent error detection, Nur A. Touba, Edward J. McCluskey

@TechReport{csl-tr-93-591,
  author = 	 "Nur A. Touba, Edward J. McCluskey",
  title = 	 "Logic synthesis for concurrent error detection",
  institution =  "Computer Systems Laboratory, Stanford University",
  year = 	 1993,
  address =	 "Techniccal Report No. CSL-TR-93-591"
}

On-line delay testing of digtal circuits, Piero Franco, Edward J. McCluskey

@TechReport{csl-tr-93-592,
  author = 	 "Piero Franco, Edward J. McCluskey",
  title = 	 "On-line delay testing of digtal circuits",
  institution =  "Computer Systems Laboratory, Stanford University",
  year = 	 1993,
  address =	 "Techniccal Report No. CSL-TR-93-592"
}

The performance advantages of integrating message passing in cache-coherent multiprocessors, Steven Cameron Woo, Jaswinder Pal Singh, John L. Hennessy

@TechReport{csl-tr-93-593,
  author = 	 "Steven Cameron Woo, Jaswinder Pal Singh, John L. Hennessy",
  title = 	 "The performance advantages of integrating message
		  passing in cache-coherent multiprocessors",
  institution =  "Computer Systems Laboratory, Stanford University",
  year = 	 1993,
  address =	 "Techniccal Report No. CSL-TR-93-593"
}

Specifying system requirements for memory consistency models, Kourosh Gharachorloo,Sarita Adve, Anoop Gupta, John Hennessy, Mark Hill

@TechReport{csl-tr-93-594,
  author = 	 "Kourosh Gharachorloo,Sarita Adve, Anoop Gupta, John
		  Hennessy, Mark Hill",
  title = 	 "Specifying system requirements for memory
		  consistency models",
  institution =  "Computer Systems Laboratory, Stanford University",
  year = 	 1993,
  address =	 "Techniccal Report No. CSL-TR-93-594"
}

Sufficient system requirements for supporting the PLPC memory model, Sarita Adve, Kourosh Gharachorloo, Anoop Gupta, John Hennessy, Mark Hill

@TechReport{csl-tr-93-595,
  author = 	 "Sarita Adve, Kourosh Gharachorloo, Anoop Gupta, John
		  Hennessy, Mark Hill",
  title = 	 "Sufficient system requirements for supporting the
		  PLPC memory model",
  institution =  "Computer Systems Laboratory, Stanford University",
  year = 	 1993,
  address =	 "Techniccal Report No. CSL-TR-93-595"
}

Models of communication latency in shared memory multiprocessors, Gregory T. Byrd

@TechReport{csl-tr-93-596,
  author = 	 "Gregory T. Byrd",
  title = 	 "Models of communication latency in shared memory
		  multiprocessors",
  institution =  "Computer Systems Laboratory, Stanford University",
  year = 	 1993,
  address =	 "Techniccal Report No. CSL-TR-93-596"
}

Performance evaluation of hybrid hardware and software distributed shared memory protocols, Rohit Chandra, Kourosh Gharachorloo, Vijayaraghavan Soundararajan, Anoop Gupta

@TechReport{csl-tr-93-597,
  author = 	 "Rohit Chandra, Kourosh Gharachorloo, Vijayaraghavan
		  Soundararajan, Anoop Gupta",
  title = 	 "Performance evaluation of hybrid hardware and
		  software distributed shared memory protocols",
  institution =  "Computer Systems Laboratory, Stanford University",
  year = 	 1993,
  address =	 "Techniccal Report No. CSL-TR-93-597"
}