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Memory management issues at the operating system level targeting high-end many-core platforms
講演者:ゲローフィ バリ(東京大学)
平成26年5月30日(金)15時〜16時30分 東京大学理学部七号館007講義室
The latest architectural trends in high-end computing, such as heterogenous platforms, massively many-core CPUs, the co-existence of alternative memory technologies with regular DRAM forming additional levels in the memory hierarchy, etc., have introduced various challenges for the current system software stack. Efficient memory management, in particular at the operating system layer, is the main focus of this talk.

First, an overview of existing studies on OS level memory management targeting many-core platforms is given. We then proceed on describing several of our recent proposals. Specifically, we discuss a scalable page table organization, called partially separated page tables (PSPT), which minimizes the cost of remote TLB invalidations on many-core CPUs. On top of PSPT, we describe a novel page replacement policy and compare its performance against standard page replacement algorithms. As part of this talk, we revisit paging based virtual memory and argue that high performance applications, in particular those that target big data processing, can suffer substantial performance degradation due to paging, despite the fact that they do not require paging's sophisticated features. Instead, a hybrid segmentation based kernel architecture is presented which can eliminate most of the cost associated with paging. Finally, we discuss a cache-line latency aware memory allocator, which exploits the differences in access latencies for different cache lines issued by separate CPU cores, and thus can improve performance of latency sensitive applications.