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FPGA-based Hardware Merge Sorter
講演者:吉瀬謙二(東京工業大学)
平成29年11月28日(火)15時〜16時30分 理学部7号館2階214講義室
Recent studies show that FPGA-based hardware merge sorters (HMSs) can achieve superior performance compared with optimized algorithms on CPUs and GPUs. The performance of any HMS is proportional to its operating frequency (F) and the number of records that can be output each cycle (E). However, all existing HMSs have a problem that F drops significantly with increasing E due to the increase of the number of levels of gates. In this talk, novel architectures for HMSs where the number of levels of gates is constant when E is increased are shown. Some HMSs adopting the proposed architectures are implemented on a Virtex-7 FPGA. The evaluation shows that the proposed HMSs achieve higher throughput than the previous state-of-the-art HMS. (This talk will be given in Japanese with English slides.)